Contribución al estudio de las interferencias electromagnéticas conducidas en circuitos integrados

This thesis is focused on the conducted electromagnetic Interference generated at Integrated Circuit (IC) Level. Recently, several electrical models have been proposed in order to describe EMI at IC level, but they have several limitations. The first drawback is that these electrical models do not take into account the wear-out mechanisms on the EMI behaviour. The wear-out mechanisms are due to the dielectric degradation when an electric stress is applied to the oxide gate. Due to this degradation, the MOSFET characteristics are shifted. Therefore, the evaluation of wear-out mechanisms allow the designers, during the IC design, to predict the circuit behaviour along its lifetime. However, the impact of these wear-out mechanisms on the conducted EMI drift at IC level has not been deeply investigated. Hence, one of the aims of this thesis will be focused on the impact of wear-out mechanisms in signal integrity and conducted EMI at IC level. Moreover, current integrated circuits have a high operation frequency. Thus, the electromagnetic noise induced on those devices presents a higher harmonic content. For this reason, the electronics industry requires electrical models to predict high frequency conducted emissions. In this sense, the other aim of this thesis will be focused on expanding the current EMI models beyond 1 GHz. The IC behaviour may be affected by temperature, as well as conducted emission levels. Therefore, the proposed electrical model will take into account the impact of temperature. The experimental results have been obtained with three integrated circuits, two of them are specific test chip designed by Freescale Semiconductor, Inc., and the third IC is a commercial circuit of Maxim Integrated Circuits. This document is structured in four chapters. Chapter 1 describes the main wear-out mechanisms and the electromagnetic compatibility at IC level. The different EMI produced at IC are explained. Also, it describes aging methods to characterize the impact of wear-out mechanisms on MOS devices. Furthermore, the EMI characterization methods are explained and different EMC electrical models are described. To confirm the accuracy of the EMC models, the ¿Feature Selective Validation¿ (FSV) technique has been used. On this chapter, the FSV method and its application on computational electromagnetism is detailed. The chapter ends with the state of the art on wear-out mechanisms and EMI at IC level. Chapter 2 analyzes the IC reliability. The IC aging of the MOSFET I-V curve characteristics is studied, for further EMI characterization of the impact of wear-out mechanisms. The experimental results are presented at the end of Chapter 2. Chapter 3 presents an electrical model to characterize the conducted emissions of an IC up to 3 GHz. This electrical model considers the impact of temperature. The proposed model is validated with experimental results and verified with the FSV method. Chapter 4 summarizes the conclusions of the thesis and the main contributions. In addition, a list of the publications derived from this thesis is included. Finally, the chapter presents the lines for future research.Esta tesis se centra en el estudio de las interferencias electromagnéticas (“Electromagnetic Interferences” o EMI) conducidas generadas a nivel de circuito integrado (CI). En la actualidad, existen modelos eléctricos para describir las EMI conducidas a nivel de CI, pero presentan ciertas limitaciones. La primera de ellas es que estos modelos no tienen en cuenta el impacto de los mecanismos de degradación sobre las EMI. Los mecanismos de degradación aparecen por el deterioro del dieléctrico debido al estrés eléctrico aplicado en el óxido de puerta. Estos mecanismos producen la variación de las características eléctricas de los dispositivos MOS. El estudio de estos efectos permite predecir, durante la etapa inicial del diseño, su impacto durante el tiempo de vida de los CI. Sin embargo, hasta la fecha, no se han llevado a cabo estudios del efecto de los mecanismos de degradación en las EMI conducidas a nivel de CI. Por lo tanto, uno de los primeros objetivos de la tesis será caracterizar el impacto de los mecanismos de degradación en la integridad de la señal y en las EMI conducidas a nivel de CI. Asimismo, los CI tienen una frecuencia de funcionamiento cada vez mayor, de modo que el ruido electromagnético generado por estos dispositivos tiene un contenido harmónico de más alta frecuencia. Es por esto que conviene tener modelos eléctricos que permitan modelizar las EMI de alta frecuencia. El segundo objetivo de la tesis consiste en modelizar las EMI conducidas más allá de la frecuencia de 1 GHz ya que los modelos actuales son válidos hasta esta frecuencia. La temperatura de funcionamiento del CI puede afectar al comportamiento del mismo, así como a los niveles de las emisiones conducidas. Por lo tanto será de interés que el modelo propuesto tenga en cuenta el impacto de la temperatura, ya que los modelos actuales únicamente son válidos para una temperatura de funcionamiento. La validación experimental se ha llevado a cabo sobre tres circuitos integrados, dos de ellos diseñados específicamente para este estudio por la empresa Freescale Semiconductor, Inc. y el tercer CI es un circuito comercial de Maxim Integrated Circuits. Este documento se compone de cuatro capítulos. El capítulo 1 empieza con la descripción de los principales mecanismos de degradación y de la compatibilidad electromagnética a nivel de circuito integrado. Se detallan las diferentes interferencias electromagnéticas que pueden producirse a nivel de circuito integrado. Se procede con la descripción de los métodos acelerados de envejecimiento para caracterizar el impacto de los mecanismos de degradación en los dispositivos MOS. Se continúa con una explicación de los métodos para caracterizar las EMI y la presentación de diferentes modelos EMC para su modelización. Para la validación de los estos modelos EMC se hace uso del método “Feature Selective Validation” (FSV). En este capítulo se da explicación al método FSV y su aplicación en el electromagnetismo computacional. Para finalizar el capítulo, se describe el estado actual de la investigación en el campo de los mecanismos de degradación y de las EMI a nivel de CI. En el capítulo 2 se analiza la fiabilidad de los CI. Se estudia el impacto de los mecanismos de degradación en el comportamiento de los transistores, para posteriormente estudiar el impacto de estos mecanismos en las EMI. El capítulo 2 se complementa con los resultados experimentales obtenidos en el laboratorio. El capítulo 3 se centra en la caracterización y el modelado de las EMI en los circuitos integrados. Se propone un modelo eléctrico para caracterizar las interferencias electromagnéticas conducidas hasta los 3 GHz y el impacto de la temperatura en las emisiones conducidas. El modelo propuesto es comprobado con medidas experimentales y verificado con el método FSV. Por último, el capítulo 4 resume las conclusiones de la tesis y las principales contribuciones. Además, en este capítulo se presenta las líneas de investigación futuras. Esta tesis se ha desarrollado dentro de una de las líneas de investigación del Grupo de Electrónica Industrial de Terrassa (“Terrassa Industrial Electronics Group” - TIEG), dentro del marco del proyecto de investigación TEC2009-09994, TEC2010-18550 y AGAUR 2009 SGR 142

Characterization and modeling of the electromagnetic emission of an ADC converter

Analog-to-digital converters (ADC) are widely used in consumer electronics, as well as aeronautic, space and automotive development fields. The ADC clock frequency has been increasing in the latest years due to the continuous downscaling in CMOS technology. This constant rising of the operating frequency implies a significant enhancement of the electromagnetic inference (EMI). Therefore, in order to predict the impact of the EMI on the electronic systems performance, electrical circuit models, involving these EMC issues, are required. In this sense, an electromagnetic model of integrated circuits has been internationally standardized (ICEM model) [1]. This model includes a passive distribution network (PDN), which presents the characteristics of propagations paths of electromagnetic noise and the internal activity (IA), which corresponds to the electromagnetic noise source that originates in switching of active devices in the integrated circuit (IC), measured according to [2]. This work addresses the characterization and modeling of a 10-bit Analog-to-Digital Converter in a 8-small outline integrate circuit (SOIC) package, according to the international standard IEC 62433-2. The ADC has a 3.3 V supply voltage, and an operating frequency of 2.8 MHz. The clock (CLK) corresponds to a square signal with a duty cycle of 50 % and the chip select (CS) is a square waveform of 100 kHz with a duty cycle of 10 %. The input voltage has been chosen to have the worst condition, (i.e. when the ADC output has the maximum number of transitions from 0 to VCC and vice versa). Fig. 1 shows the spectrum of the ADC’s IA measured according to EN 61967-4. The spectrum contains several harmonics due to the CLK and CS signals. The first harmonic is located at 1.4 MHz which corresponds to the frequency of the ADC serial output, and then successive harmonics at even and pair frequencies are produced. All the ADC serial output harmonics present sidebands due to the CS signal. Fig. 2 depicts the return losses parameter (S11) in the power supply pin, which has been obtained by means of a vector network analyzer. The information obtained with S11 is related with the input impedance of the integrated circuit and the characteristics of propagation paths. From these dates, the ICEM model of the ADC converter has been obtained.Peer ReviewedPostprint (published version

Modelling and experimental verification of the impact of negative bias temperature instability on CMOS inverter

Published in Microelectronics Reliability, Volume 49, Issues 9-11, September-November 2009, Pages 1048-1051The effects of negative bias temperature instability (NBTI) on the performance of a CMOS inverter have been investigated by means of both simulation and experimental methods. The simulation of NBTI effects on CMOS inverter has been done by shifting the pFET Vtho BSIM parameter. The results show that NBTI shifts the inverter transfer curve, reduces the low noise margin and current consumption but increases the high noise margin. A good agreement between simulation and experimental results has been obtained. Therefore, it can be assumed that the effect of NBTI on CMOS circuits can be mainly predicted by shifting the Vtho pFET parameter.Peer ReviewedPostprint (author’s final draft

Performance assessment of a wide-bandgap-semiconductor dual-active-rridge converter for electrical vehicles

Dc-dc converters can be found in different kinds of electric vehicles (EVs). Their main function is to accommodate voltages and currents to the motor or other EV systems requirements. The use of wide-bandgap (WBG) devices can improve the efficiency of silicon-based power converters, qualifying also for higher switching frequencies. In this article the features of a dual active bridge (DAB) converter are studied. The high voltage side of the DAB is implemented with Silicon Carbide (SiC) MOSFETs. For the low voltage side two types of devices are used: either Gallium Nitride (GaN) enhancement high-electronmobility transistors (e-HEMTs) or SiC MOSFETs. The influence of switching frequency and output power on the efficiency are evaluated. The parallel connection of GaN devices is proposed to overcome the device current limits and thus increase the overall DAB converter output power. A feedback controller has been designed to reduce the effects on the output voltage of load changes. The DAB converter evaluation has been realized by using MATLAB/Simulink and PLECS software.This work was supported by the Industrial Doctorate Plan of the Secretaria d’Universitats i Recerca del Departament d’Empresa i Coneixement de la Generalitat de Catalunya, and the Ministerio de Ciencia, Innovación y Universidades of Spain within the project PID2019-111420RB-I00.Peer ReviewedPostprint (author's final draft

Effect of the heat dissipation system on hard-switching GaN-based power converters for energy conversion

The design of a cooling system is critical in power converters based on wide-bandgap (WBG) semiconductors. The use of gallium nitride enhancement-mode high-electron-mobility transistors (GaN e-HEMTs) is particularly challenging due to their small size and high power capability. In this paper, we model, study and compare the different heat dissipation systems proposed for high power density GaN-based power converters. Two dissipation systems are analysed in detail: bottom-side dissipation using thermal vias and top-side dissipation using different thermal interface materials. The effectiveness of both dissipation techniques is analysed using MATLAB/Simulink and PLECS. Furthermore, the impact of the dissipation system on the parasitic elements of the converter is studied using advanced design systems (ADS). The experimental results of the GaN-based converters show the effectiveness of the analysed heat dissipation systems and how top-side cooled converters have the lowest parasitic inductance among the studied power converters.This work was supported by the Industrial Doctorates Plan of the Secretaria d’Universitats i Recerca del Departament d’Empresa i Coneixement de la Generalitat de Catalunya, the Centro para el Desarrollo Tecnológico Industrial (IDI-20200864), and the Ministerio de Ciencia, Innovación y Universidades of Spain within the project PID2019-111420RB-I00Peer ReviewedPostprint (published version

Common-mode voltage mitigation strategies using sigma-delta modulation in five-phase VSIs

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Various sigma–delta ( S ¿ ) modulation techniques for reducing the maximum peak-to-peak amplitude of common-mode voltage (CMV) by 80% in a five-phase, high-frequency voltage source inverter (VSI) are proposed and evaluated in this article. These techniques are based on choosing a set of vectors that limits the CMV amplitude. Operating the VSI under high-frequency pulsewidth modulations (PWM) generates a large number of changes in the CMV levels, which leads to common-mode currents (CMCs) and conducted electromagnetic interferences (EMIs). The proposed modulation techniques achieve the following: 1) High-efficiency converter operation and output voltage with low total harmonic distortion (THD); 2) an 80% reduction in CMV peak-to-peak amplitude; 3) a decrease in the number of the CMV transitions, thus reducing the CMCs; and 4) a decrease in the conducted EMI amplitude. The use of single-loop and double-loop S ¿ modulators is analyzed by means of Matlab/Simulink and PLECS simulations. The implementation of the proposed modulation techniques has been experimentally evaluated using a five-phase VSI with silicon carbide semiconductors. In order to demonstrate the improved performance, the results obtained are compared with those of other PWM and space vector modulation techniques that also mitigate the CMV amplitude by 80% but lack the other improvements.Peer ReviewedPostprint (author's final draft

Constant common-mode voltage strategies using sigma-delta modulators in five-phase VSI

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper proposes and studies different sigma-delta () modulation strategies for obtaining a constant common-mode voltage (CMV) by eliminating the CMV level transitions in a five-phase voltage source inverter (VSI). These techniques are based on choosing vectors that generate a constant CMV with values of 0.1Vdc or 0.1Vdc. Because of the high-switching frequencies used with wide-bandgap semiconductors, pulse-width modulation (PWM) techniques continually generate high dv/dt values. Therefore, the proposal to combine a modulation strategy with vector selections achieves: 1) a constant CMV level due to the elimination of its level transitions; 2) a reduction in conducted electromagnetic interference; and 3) a high-efficiency converter operation. The average number of switching per transistor of the VSI is analyzed using the results from Matlab/Simulink and PLECS simulations. Experimental results are obtained by applying the proposed modulation strategies on a VSI with silicon carbide (SiC) MOSFETs. The results demonstrate the achievement of the aforementioned features.This work was supported in part by the Ministerio de Ciencia, Innovacion y Universidades of Spain within ´ the TRA2016-80472-R and PID2019-111420RB-I00 projects, the CONACYT of Mexico under scholarship 496458, Secre- ´ taria d’Universitats i Recerca del Departament d’Empresa i Coneixement de la Generalitat de Catalunya.Peer ReviewedPostprint (author's final draft

Efficiency comparison of power converters based on SiC and GaN semiconductors at high switching frequencies

© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Hard-switching voltage source converters (VSC) based on wide-bandgap (WBG) devices surpass their silicon equivalents in every aspect. Nevertheless, at high switching frequencies, the efficiency significantly differs depending on the WBG semiconductor used. This article presents an extensive comparison between gallium nitride (GaN), and silicon carbide (SiC) devices in terms of efficiency. The impact of the switching frequency is evaluated for each semiconductor using two modulation techniques: the classical space vector pulse width modulation (SVPWM) technique, and the innovative hexagonal sigma-delta modulation (H-S¿). The performance and losses of both WBG technologies are analysed here using Matlab/Simulink and PLECS. Experimental results performed on two VSC converters, one based on SiC devices and the other made using GaN transistors, show the influence of the semiconductor technology and the modulation strategy on the efficiency at high switching frequenciesPeer ReviewedPostprint (published version

Fast-processing sigma-delta strategies for three-phase wide-bandgap power converters with common-mode voltage reduction

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The electromagnetic compatibility of wide-bandgap (WBG) power converters can be greatly improved using spread-spectrum modulation techniques. This article proposes a family of reduced common-voltage sigma–delta modulations (RCMV- S¿ ) for voltage source converters (VSC) that use gallium nitride (GaN) semiconductors. Specifically, this article proposes three new techniques: two reduced-state sigma–delta modulations (RS- S¿1 &2), and an active sigma–delta strategy (A- S¿ ). The proposed modulation techniques reduce or eliminate the common-mode voltage (CMV) dv/dt transitions and suppress the noise spikes in the conducted electromagnetic interference spectrum. Furthermore, this article proposes the use of fast-processing quantizers for RCMV- S¿ techniques as well as for hexagonal sigma–delta (H- S¿ ). These quantizers use a novel calculation methodology that simplifies the implementation of the proposed modulations and considerably reduces their computational cost. The performance and the total harmonic distortion (THD) of RCMV- S¿ techniques are analyzed here using MATLAB/Simulink and PLECS. Experimental results performed on a VSC converter that uses GaN e-HEMTs show how RCMV- S¿ techniques considerably improve electromagnetic compatibility and exhibit similar efficiencies and THD to those of H- S¿ .This work was supported by the Industrial Doctorates Plan of the Secretaria d’Universitats i Recerca del Departament d’Empresa i Coneixement de la Generalitat de Catalunya, the Centro para el Desarrollo Tecnológico Industrial (IDI-20200864), and in part by the Ministerio de Ciencia, Innovación y Universidades of Spain under Project PID2019-111420RB-I00.Peer ReviewedPostprint (published version